parallel input serial output shift register vhdl code

To properly synchronize an external trigger or slow clock to the 50MHz domain would typically take 20-40ns: one clock edge to sample the external signal, the next clock edge to use the single sampled value across all dependent registers. It must be the generation of the tx_clk strobe where most of the delay is felt. Since your description suggests both tx_clk and frame_end are synchronized to the 50MHz and tx_clk occurs 1 out of every 10 clocks, a delay in frame_end would cause a 200ns additional output delay.

The clk edge produces a txout when txclk is active while in the idle state. To see where all the delays are, you'd have to show how the tx_clk strobe and frame_end are generated since the shifter you describe has no more delays beyond what those signals cause. Is tx_clk a 5 MHz strobe (1 high in 10 periods) in the 50MHz time domain? If not, some assumptions here are invalid. What can be done in order to minimize the delay? I can see delay of ~ 80 nsec, between the external clock and the output data. I have designed this register and synchonized the 5 MHz external trigger (pseudo clock txclk) to the 50 MHz clock. The output serial data should be synchronized to the external clock (5 MHz). The external trigger and the board clock ( 50 MHz ) are not synchonized. My board clock is 50 MHz and I also have an external trigger ( ~ 5 MHz, pseudo clock). Would like to design a parallel in serial out shift register.

Parallel input serial output shift register vhdl code